A SYSTEMC language extension for high-level reconfiguration modelling

The ongoing trend towards development of parallel software and the increased flexibility of state-of-the-art programmable logic devices are currently converging in the field of reconfigurable hardware. On the other hand there is the traditional hardware market, with its increasingly short development cycles, which is mainly driven by high-level prototyping of products. This paper presents a library for modelling reconfiguration in the leading high-level system description language SystemC combining IP reuse and high-level modelling with reconfiguration. Details on the underlying simulation engine are given, which allows safe disabling and re-enabling of all process types without altering the kernel. Novel control statements and internal techniques that allow safe usage of process controlling in conjunction with standard SystemC language constructs are presented. A real world case study using the presented library proves its applicability.