DocumentCode :
3042652
Title :
Modeling of custom-designed arithmetic components for ABL normalization
Author :
Pavlenko, Evgeny ; Wedler, Markus ; Stoffel, Dominik ; Kunz, Wolfgang ; Wienand, Oliver ; Karibaev, Evgeny
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Kaiserslautern, Kaiserslautern
fYear :
2008
fDate :
23-25 Sept. 2008
Firstpage :
124
Lastpage :
129
Abstract :
Arithmetic bit-level (ABL) normalization has been proven a viable approach to formal property checking of datapath designs. It is applicable where arithmetic components and sub-components can be identified at the register-transfer (RT) level of the design and the property. This paper extends the applicability of ABL normalization to cases where some of the arithmetic components are custom-designed entities, e.g., specified using Boolean equations or gates. We transform these entities into ABL building blocks using Reed-Muller expressions as an intermediate representation. We show how Boolean logic expressed in Reed-Muller form can be automatically transformed into ABL components so that such logic blocks can be treated together with the remaining ABL components in a subsequent normalization run. The approach is evaluated on a number of industrial designs generated by a commercial arithmetic module generator.
Keywords :
Boolean functions; digital arithmetic; logic design; logic testing; ABL normalization; Boolean logic; Reed-Muller expression; arithmetic bit-level normalization; arithmetic component; datapath design; formal property checking; logic block; register-transfer level; Automatic logic units; Boolean functions; Circuit synthesis; Data mining; Digital arithmetic; Equations; Mathematical model; Mathematics; Robustness; Surface-mount technology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Specification, Verification and Design Languages, 2008. FDL 2008. Forum on
Conference_Location :
Stuttgart
Print_ISBN :
978-1-4244-2264-7
Type :
conf
DOI :
10.1109/FDL.2008.4641433
Filename :
4641433
Link To Document :
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