DocumentCode :
3042678
Title :
EXOP (Extended Operation): A new logical fault model for digital circuits
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Electr. & Comput. Eng. Dept., Iowa Univ., Iowa City, IA, USA
fYear :
1993
fDate :
22-24 June 1993
Firstpage :
166
Lastpage :
175
Abstract :
A gate-level fault model for digital circuits is proposed that generalizes previous models and is expected to model defects not included in other fault models. Theoretical discussions and experimental results are presented to show the effectiveness of a test set for the new fault model in achieving very high coverage of commonly used single and multiple faults. It is shown that test generation for this model can be done by a simple reordering of a stuck-at fault test set (possibly repeating some of the stuck-at tests). Reordering is based on defining a graph over the set of all stuck-at tests and finding an Euler cycle in the graph in time which is polynomial in the number of tests.
Keywords :
digital circuits; EXOP; Euler cycle; Extended Operation; digital circuits; gate-level fault model; logical fault model; simple reordering; stuck-at fault test set; test generation; Circuit faults; Circuit testing; Cities and towns; Delay; Digital circuits; FETs; Fault detection; Polynomials; Semiconductor device modeling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Fault-Tolerant Computing, 1993. FTCS-23. Digest of Papers., The Twenty-Third International Symposium on
Conference_Location :
Toulouse, France
ISSN :
0731-3071
Print_ISBN :
0-8186-3680-7
Type :
conf
DOI :
10.1109/FTCS.1993.627320
Filename :
627320
Link To Document :
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