A 35-GHz 20- mu m/sup 2/ self-aligned PNP technology for ultra-high-speed high-density complementary bipolar ULSIs

Author

Washio, K. ; Shimamoto, H. ; Nakamura, T.

Author_Institution

Hitachi Ltd., Tokyo, Japan

fYear

1992

fDate

2-4 June 1992

Firstpage

64

Lastpage

65

Abstract

An ultra-high-speed high-density self-aligned pump technology for complementary bipolar ULSIs which is fully compatible with the npn process is discussed. A low sheet-resistance p/sup +/ buried layer and an extrinsic n/sup +/ polysilicon layer with U-grooved isolation enable the transistor size to be scaled down to about 20 mu m/sup 2/. A shallow emitter junction depth of 45 nm and narrow base width of 30 nm improve maximum cutoff frequency to 35 GHz. The power dissipation of a pnp pull-down complementary emitter-follower ECL circuit for the loaded case is calculated to be reduced to 1/5 compared with the conventional ECL circuit.<>

Keywords

VLSI; bipolar integrated circuits; bipolar transistors; emitter-coupled logic; integrated circuit technology; solid-state microwave devices; 35 GHz; U-grooved isolation; extrinsic n/sup +/ polysilicon layer; low sheet-resistance p/sup +/ buried layer; maximum cutoff frequency; narrow base width; power dissipation; pull-down complementary emitter-follower ECL circuit; self-aligned PNP technology; self-aligned pump technology; shallow emitter junction depth; ultra-high-speed high-density complementary bipolar ULSIs; Artificial intelligence; Circuits; Delay effects; Electrons; Frequency; Paper technology; Silicon; Sun; Tin; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on

Conference_Location

Seattle, WA, USA

Print_ISBN

0-7803-0698-8

Type

conf

DOI

10.1109/VLSIT.1992.200692

Filename

200692