• DocumentCode
    3042870
  • Title

    A model driven development approach for implementing reactive systems in hardware

  • Author

    Wang, Zhonglei ; Herkersdorf, Andreas ; Merenda, Stefano ; Tautschnig, Michael

  • Author_Institution
    Lehrstuhl fur Integrierte Syst., Tech. Univ. Munchen, Munchen
  • fYear
    2008
  • fDate
    23-25 Sept. 2008
  • Firstpage
    197
  • Lastpage
    202
  • Abstract
    To deal with the increasing complexity of digital systems, the model driven development approach has proven to be beneficial. This paper presents a model driven hardware design process that is dedicated to reactive embedded systems. The approach is based on the component language (COLA), a synchronous data flow language with formal semantics. COLA follows the hypothesis of perfect synchrony. Models thus do not assume specific timing properties and remain deterministic as long as data flow requirements are retained. This is an essential feature for modeling safety-critical systems. Further, the well-defined semantics not only allows that the resulting models can be formally reasoned about, but is also the key to translation to domain-specific languages. This paper describes the approach of translating the models to VHDL descriptions from their graphical representations. As COLA is well-adapted to both data flow description and control automata, the generated VHDL code can be synthesized to very efficient FPGA circuits, comparable to that synthesized from hand-written VHDL code according to our case study.
  • Keywords
    data flow analysis; embedded systems; hardware description languages; parallel languages; safety-critical software; FPGA circuits; VHDL descriptions; component language; data flow requirements; domain-specific languages; formal semantics; model driven hardware design process; reactive embedded systems; safety-critical systems; synchronous data flow language; Automata; Automatic generation control; Circuit synthesis; Digital systems; Domain specific languages; Embedded system; Field programmable gate arrays; Hardware; Process design; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Specification, Verification and Design Languages, 2008. FDL 2008. Forum on
  • Conference_Location
    Stuttgart
  • Print_ISBN
    978-1-4244-2264-7
  • Type

    conf

  • DOI
    10.1109/FDL.2008.4641445
  • Filename
    4641445