Title :
Formal specification of delta MINs for MPSOC in the ACL2 logic
Author :
Elleuch, Maissa ; Aydi, Yassine ; Abid, Mohamed
Author_Institution :
CES-Nat. Eng. Sch. of Sfax, Sfax
Abstract :
The design of modern multiprocessor systems-on-chip has performance constraints which must be satisfied by the interconnection architecture. multistage interconnection networks, also denoted MINs, seem to be a promising alternative for solving the problems of on-chip communications. This paper presents a formal specification of the Delta multistage interconnection networks for MPSoCs in the ACL2 logic. This work is based on a generic model for networks on chip (GeNoC).
Keywords :
formal specification; multiprocessing systems; multistage interconnection networks; system-on-chip; ACL2 logic; GeNoC; MPSOC; delta MIN; formal specification; interconnection architecture; multiprocessor systems-on-chip; multistage interconnection networks; networks-on-chip; Communication switching; Design engineering; Formal specifications; LAN interconnection; Logic design; Multiprocessing systems; Multiprocessor interconnection networks; Network-on-a-chip; Routing; Switches;
Conference_Titel :
Specification, Verification and Design Languages, 2008. FDL 2008. Forum on
Conference_Location :
Stuttgart
Print_ISBN :
978-1-4244-2264-7
DOI :
10.1109/FDL.2008.4641461
