Exploiting loop-level parallelism on multi-core architectures for the wimax physical layer

Multiprocessor system-on-chip (MPSoC) architectures are increasingly being adopted in the design of emerging complex embedded systems. This paper introduces a new application mapping technique for MPSoC architectures using a case study. The technique incorporates profiling-driven task partitioning, task transformations, loop level partitioning and memory architecture aware data mapping to reduce system execution time. Experiments are conducted to evaluate the technique by implementing the WiMAX physical layer on several multi-core architectures based on newly emerging dynamically reconfigurable processor cores. The results demonstrate that the proposed technique is able to generate high-quality mappings of realistic applications on the target architecture, achieving up to 4.92x speedup by employing only five dynamically reconfigurable processor cores.