Nanoscale on-chip decoupling capacitors

A distributed on-chip decoupling capacitor network is proposed in this paper to replace one large capacitor. A system of distributed on-chip decoupling capacitors is shown to provide an efficient solution for providing the required on-chip decoupling capacitance under existing technology constraints. In a system of distributed on-chip decoupling capacitors, each capacitor is sized based on the parasitic impedance of the power distribution grid. To be effective, on-chip decoupling capacitors should be charged before the next switching cycle. A design space for estimating the maximum parasitic resistance of the power distribution grid during discharge and the charging phase has been determined. Related simulation results for typical values of the on-chip parasitic resistance are also presented. An analytic solution is shown to provide accurate parameters of the distributed system. The worst case error is 0.002% during discharge and 0.08% during the charging phase as compared to SPICE.