A multi-wire error correction scheme for reliable and energy efficient SOC links using hamming product codes

Author

Fu, Bo ; Ampadu, Paul

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Rochester, Rochester, NY

fYear

2008

fDate

17-20 Sept. 2008

Firstpage

59

Lastpage

62

Abstract

A multi-wire error correction scheme, which combines Hamming product codes with type-II hybrid ARQ, is proposed for reliable and energy efficient SoC links. Also, a hard decision iterative decoding method, which can achieve the maximum error correction capability of Hamming product codes, is proposed. Simulation results show an improvement of up to four orders of magnitude in residual flit-error rate for multi-wire errors. For a given system reliability requirement, the proposed error control scheme can achieve 35% energy improvement over other error correction codes.

Keywords

Hamming codes; automatic repeat request; error correction codes; integrated circuit reliability; iterative decoding; system-on-chip; Hamming product codes; energy efficient SOC links; hard decision iterative decoding; maximum error correction capability; multiwire error correction; multiwire errors; reliable efficient SOC links; residual flit-error rate; type-II hybrid ARQ; Block codes; Encoding; Energy efficiency; Error correction; Error correction codes; Iterative decoding; Parity check codes; Power system interconnection; Product codes; Redundancy;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2008 IEEE International

Conference_Location

Newport Beach, CA

Print_ISBN

978-1-4244-2596-9

Electronic_ISBN

978-1-4244-2597-6

Type

conf

DOI

10.1109/SOCC.2008.4641480

Filename

4641480