Title :
Self-exercising self testing k-order comparators
Author :
Kavousianos, X. ; Nikolos, D.
Author_Institution :
Dept. of Comput. Eng. & Inf., Patras Univ., Greece
fDate :
27 Apr-1 May 1997
Abstract :
In this paper we give a systematic method to design self-exercising (SE) self testing k-order comparators. The k-order comparator is defined as a combinational circuit that compares two operands and decides if these differ in less than k bits. According to this definition the usual equality comparator is the 1st-order comparator. Also in this paper we discuss the applicability of the k-order comparators in the implementation of (k-1)-EC/AUED, (k-1)-EC/d-ED/AUED, (k-1)-EC/d-UED and (k-1)-EC/d-ED/f-UED codes as well as in the design of a fault tolerant cache memory and broadcast networks
Keywords :
VLSI; built-in self test; cache storage; combinational circuits; comparators (circuits); error correction codes; error detection codes; fault tolerant computing; broadcast networks; combinational circuit; equality comparator; error correction codes; error detection codes; fault tolerant cache memory; self testing k-order comparators; self-exercising comparators; Automatic testing; Broadcasting; Built-in self-test; Cache memory; Circuit faults; Combinational circuits; Design engineering; Design methodology; Error correction codes; Informatics;
Conference_Titel :
VLSI Test Symposium, 1997., 15th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-7810-0
DOI :
10.1109/VTEST.1997.600275
