Area efficient delay-insensitive and differential current sensing on-chip interconnect

We present a noise and delay variations robust high-performance on-chip interconnect based on a new area and power efficient integration of self-timed delay-insensitive data transfer and differential current sensing signaling. Only half number of wires are required compared to conventional integration of the two schemes, making it both area and power efficient. At 5 mm wire length a throughput of 1.34 Gbps has been achieved and 24% power savings have been gained. The interconnect is designed and simulated using Cadence Spectre with a 65nm CMOS technology.