FPGA/NIOS implementation of an adaptive FIR filter using linear prediction to reduce narrow band RFI for radio detection of cosmic rays

We present the FPGA/NIOS^® implementation of an adaptive finite impulse response (FIR) filter based on linear prediction to suppress radio frequency interference (RFI). This technique will be used for experiments that observe coherent radio emission from extensive air showers induced by ultra-high-energy cosmic rays. These experiments are designed to make a detailed study of the development of the electromagnetic part of air showers. Therefore, these radio signals provide information that is complementary to that obtained by water-Cherenkov detectors which are predominantly sensitive to the particle content of an air shower at ground. The radio signals from air showers are caused by the coherent emission due to geomagnetic and charge-excess processes. These emissions can be observed in the frequency band between 10 - 100 MHz. However, this frequency range is significantly contaminated by narrow-band RFI and other human-made distortions. A FIR filter implemented in the FPGA logic segment of the front-end electronics of a radio sensor significantly improves the signal-to-noise ratio. In this paper we discuss an adaptive filter, which is based on linear prediction. The coefficients for the linear predictor are dynamically refreshed and calculated in the virtual NIOS^® processor, which is implemented in the same FPGA chip. The Levinson recursion, used to obtain the filter coefficients, is also implemented in the NIOS^® and is partially supported by direct multiplication in the DSP blocks of the logic FPGA segment. Tests confirm that the linear predictor can be an alternative to other methods involving multiple time-to-frequency domain conversions using an FFT procedure. These multiple conversions draw heavily on the power consumption of the FPGA and are avoided by the linear prediction approach. The FIR filter has been successfully tested in the Altera^® development kits with the the EP4CE115F29C7 - rom the Altera^® Cyclone^® IV family and the EP3C120F780C7 from the Cyclone^® III family at a 170 MHz sampling rate, a 12-bit I/O resolution, and an internal 30-bit dynamic range. Most of the slow floating-point NIOS^® calculations have been moved to the FPGA logic segments as extended fixed-point operations, which significantly reduced the refreshing time of the coefficients used in the linear prediction.