Title :
Exact probabilistic analysis of error detection for parity checkers
Author_Institution :
Armenian Nat. Academy of Sci., American Univ. of Armenia, Yerevan, Armenia
fDate :
27 Apr-1 May 1997
Abstract :
Error detection probability and latency of the parity checker with respect to single stuck-at faults in the circuit under check (CUC) are calculated analytically. A notion of “multi-output supergate” is introduced for multi-output combinational CUC generalizing the formerly known notion of (single-output) supergate. “Restricted” observabilities and detectabilities are calculated for each line in the CUC with respect to non-empty subsets of outputs of the CUC. The method may be easily extended for other concurrent checkers as well
Keywords :
combinational circuits; error detection; fault diagnosis; logic testing; parity; probability; circuit under check; combinational CUC; concurrent checker; error detection; latency; multi-output supergate; parity checker; probabilistic analysis; restricted detectability; restricted observability; single stuck-at fault; Circuit analysis; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Delay; Density measurement; Error analysis; Observability; Probability;
Conference_Titel :
VLSI Test Symposium, 1997., 15th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-7810-0
DOI :
10.1109/VTEST.1997.600276
