Pseudo parallel architecture for AES with error correction

Cryptographic hardware design is facing many challenges because of conflicting requirements such as fault attack tolerance and low power consumption. Therefore, it is important to explore different architectures that meet the above challenges. Towards this, in this paper we present different advanced encryption standard (AES) implementation with varying complexity. Specifically, we analyzed the architectural complexity with different data paths. Moreover, we incorporated error correction in sequential elements to mitigate the fault attacks and analyzed the area complexity.