DocumentCode
3043944
Title
A novel 5.46 mW H.264/AVC video stream parser IC
Author
Brown, Michael ; Hsu, Kenneth W.
Author_Institution
Intel Corp., Fort Collins, CO
fYear
2008
fDate
17-20 Sept. 2008
Firstpage
197
Lastpage
200
Abstract
This paper presents a 5.46 mW H.264/AVC Video Stream Parser implemented in 65 nm. The differences between targeting a video stream parser architecture for a 65 nm CMOS ASIC and a Virtex 5 FPGA are also compared. Overall, the ASIC implementations showed higher performance and lower area than an FPGA, with a 60% increase in performance and 6x decrease in area.
Keywords
application specific integrated circuits; grammars; integrated circuits; video coding; video streaming; CMOS ASIC; H.264/AVC video stream parser; Virtex 5 FPGA; power 5.46 mW; size 65 nm; video stream parser architecture; Application specific integrated circuits; Automatic voltage control; CMOS technology; Decoding; Encoding; Field programmable gate arrays; Frequency; Streaming media; Video compression; Video sequences;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2008 IEEE International
Conference_Location
Newport Beach, CA
Print_ISBN
978-1-4244-2596-9
Electronic_ISBN
978-1-4244-2597-6
Type
conf
DOI
10.1109/SOCC.2008.4641510
Filename
4641510
Link To Document