DocumentCode
3043955
Title
A low-power design of quantization for H.264 video coding standard
Author
Michael, Michael N. ; Hsu, Kenneth W.
Author_Institution
Intel Corp., Folsom, CA
fYear
2008
fDate
17-20 Sept. 2008
Firstpage
201
Lastpage
204
Abstract
Low-power quantization architecture for H.264/AVC is presented and implemented on VLSI. The multiplication operation is replaced with shifts and additions. Similar designs were proposed which had 75.2% area and 76.3% power on average saved compared with original H.264 quantization scheme, along with an error percent within 6.4% range. In this paper, the improved architecture has error percent within 2.4% range. The power and area saved on average is ~8% compared to designs of similar architecture.
Keywords
VLSI; quantisation (signal); video coding; H.264/AVC; VLSI; addition operation; low-power quantization architecture; shift operation; video coding standard; Automatic voltage control; Floating-point arithmetic; Hardware; MPEG 4 Standard; MPEG standards; Quadratic programming; Quantization; Very large scale integration; Video coding; Video compression;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2008 IEEE International
Conference_Location
Newport Beach, CA
Print_ISBN
978-1-4244-2596-9
Electronic_ISBN
978-1-4244-2597-6
Type
conf
DOI
10.1109/SOCC.2008.4641511
Filename
4641511
Link To Document