ROM-less DDFS using non-equal division parabolic polynomial interpolation method

A direct digital frequency synthesizer (DDFS) based on a non-equal division parabolic polynomial interpolation method is proposed in this paper. To attain high spurious free dynamic range (SDRF) and reduce area cost, a parabolic polynomial interpolation method is adopted in the proposed design to replace conventional ROM-based phase-to-sine mapper methods. Particularly, the left 1/4 of the phase range is approximated using a low-curvature parabolic curve. The proposed design is manufactured using a standard 0.18 μm CMOS technology. The maximum output frequency is 50 MHz, the core area is 1.4528 mm², and the spurious free dynamic range (SFDR) is 68.67 dBc. The proposed DDFS outperforms prior works´ SFDR and energy efficiency.