Using DSP techniques to model analog IO buffers for serial links

Data-rates for serial links like PCIe3.0, 10GKR Ethernet, and SATA, go up to several Giga-bits/second. As the transmission data rates increase, the signal strength at the receiver side decreases due to channel loss, Inter-Symbol-Interference (ISI), crosstalk, and reflections. The Input-Output (IO) buffers are, therefore, designed with inbuilt equalization circuits to recover clock and data at the receiver. In order to verify the serial link performance, one needs to simulate the PCB/Package channels with IO buffers. Capturing BER at millions of bits, requires days and weeks of simulations using standard SPICE. To accelerate this analysis, it is important to model the transistor-level IO buffers as DSP algorithms representing the equalization. This paper presents the DSP techniques used in modeling the equalization for Analog Buffers for multi-giga-bit (Gbps) serial links.