Title :
Low-power floating bitline 8-T SRAM design with write assistant circuits
Author :
Yang, Hao-I ; Lai, Ssu-Yun ; Hwang, Wei
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu
Abstract :
Low power SRAM plays a key important role on SoC designs. In this paper, low-power floating bitline Read/Write scheme and Write assistant circuits are proposed. Read/Write replica circuits are also designed for wide-voltage range operations. A 32-Kb SRAM subarray is implemented in UMC 90 nm CMOS technology. It can operate at 1 GHz when Vdd is 1 V and at 143 MHz when Vdd is 0.5 V. Moreover, it consumes around 6.6 mW to 670 uW during access cycles.
Keywords :
CMOS memory circuits; SRAM chips; integrated circuit design; low-power electronics; CMOS technology; SoC design; low power SRAM; low-power floating bitline 8-T SRAM design; low-power floating bitline read/write scheme; read/write replica circuits; wide-voltage range operations; write assistant circuits; CMOS technology; Design engineering; Frequency; Information systems; Integrated circuit technology; Microelectronics; Packaging; Power engineering and energy; Random access memory; Voltage;
Conference_Titel :
SOC Conference, 2008 IEEE International
Conference_Location :
Newport Beach, CA
Print_ISBN :
978-1-4244-2596-9
Electronic_ISBN :
978-1-4244-2597-6
DOI :
10.1109/SOCC.2008.4641519
