A framework of architectural synthesis for dynamically reconfigurable FPGAs

Reconfiguration latency is an important factor which impacts the system performance in the reconfigurable computing design. In this paper, a framework is proposed that presents a novel approach for an optimal implementation of algorithms on FPGA based reconfigurable system. The method optimizes the temporal partitioning by performing a similar-rate-computing-based architectural synthesis. It gives the possibility to merge the related partitions during the implementation of a target architecture by the architectural synthesis based on reusing of the common task. Our approach proposes a final solution based on the computation of the mutual similar rate (M.S.R.) for a RTR implementation with a synthesis option. The proposed approach attempts to reduce the number of the temporal partitions for minimizing the overall execution time. An example is presented to illustrate this novel approach. With the architectural synthesis, the number of partition was decreased. The results demonstrate that are capable and efficient for an optimized implementation in the reconfigurable design.