A spread spectrum clock generator using digital modulation scheme

Author

Hwang, Chorng-Sii ; Li, Huan-Chun ; Tsao, Hen-Wai

Author_Institution

Dept. of Electr. Eng., Nat. Yunlin Univ. of Sci. & Technol., Douliou

fYear

2008

fDate

17-20 Sept. 2008

Firstpage

337

Lastpage

340

Abstract

This paper describes a new architecture of the spread-spectrum clock generator (SSCG) using direct digital modulation scheme on VCO. Differing from the conventional technique by altering the control voltage of VCO, the modulating operation is performed by the selection of multi-band VCO. The proposed SSCG test chip has been fabricated by CMOS 0.18mum 1P6M process. The operating frequency range is within 680~1,080MHz with the center-spread setting of 0.5% and 1%. The chip area is 0.68mm². The peak reduction at 800MHz output clock can achieve 10.61dB and 12.52dB for ratios of 0.5% and 1%, respectively. The power consumption is 12mW at 800MHz.

Keywords

CMOS integrated circuits; UHF integrated circuits; phase locked loops; signal generators; spread spectrum communication; voltage-controlled oscillators; CMOS process; PLL-based clock generator; VCO; center-spread setting; direct digital modulation scheme; frequency 680 MHz to 1.080 MHz; power 12 mW; power consumption; size 0.18 mum; spread spectrum clock generator; voltage controlled oscillator; Clocks; Counting circuits; Digital modulation; Filters; Frequency conversion; Frequency modulation; Phase locked loops; Spread spectrum communication; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2008 IEEE International

Conference_Location

Newport Beach, CA

Print_ISBN

978-1-4244-2596-9

Electronic_ISBN

978-1-4244-2597-6

Type

conf

DOI

10.1109/SOCC.2008.4641540

Filename

4641540