All digital time-to-digital converter using single delay-locked loop

This work presents an all digital time to digital converter (TDC) utilizing two-step Vernier delay chain. The sampling phases are generated using a single delay-locked loop (DLL). The design includes an adjustable resolution for obtaining small area and low power dissipation and can be applied as a high resolution frequency to digital converter and jitter measurement system. The design has an adaptive resolution between 1.6 ps ~ 16 ps. The detectable period range is between 0.4 ns ~2.01 ns equivalent to 500 MHz ~ 2.5 GHz frequency range, respectively. The circuit is designed using a 0.18 mum CMOS process with a core area of 0.547 times 0.271 mm². The power dissipation is 6.84 mW at 1.8 V supply voltage.