Abstract :
The understanding of the noise coupling phenomena is essential to semiconductor design engineers who must deal with the challenges of integrating more and more functionality on a single chip. This tutorial provides a practical approach to the analysis of noise coupling mechanisms, the implementation of efficient suppression techniques, and the simulation of noise coupling in various stages of the design flow. The noise generation, propagation, and reception are analyzed at the physical structures of devices, chip substrates, and packages. Various suppression techniques are presented, emphasizing their advantages and limitations. In addition to conventional techniques, circuit level compensation methods and design examples are presented and analyzed. The noise coupling simulation in post-layout, pre-layout, and architectural stages of design is discussed, emphasizing the advantages and limitations specific to each of these stages. A practical approach for modeling the noise coupling early in the architectural stages of the design is also presented.
