An architecture for an unattended radar signal processor

An architecture for an unattended radar signal processor is developed which satisfies the conflicting requirements of high performance, reliability, and maintainability; versus low power consumption, cost, and risk. The signal processing problem is divided into coherent processes associated with filtering and pulse compression and noncoherent processes associated with automatic detection and mapping. In coherent processing, higher speed (2 MHz) linear or vector functions are realized, whereas in noncoherent processing slower speed (100 kHz) nonlinear functions are realized. The algorithmic and implementation approach for the processor and each function is optimized by means of a weighting criterion which emphasizes performance and reliability but includes evaluation of cost, maintainability, risk, and power consumption. The resulting processor consists of a digital LSI/MSI special purpose design for the coherent processes and a custom microprocessor-based implementation using firmware functions for the noncoherent processes.