A microprogrammed signal processor

The implementation of a microprogrammable signal processor which utilizes a bit-sliced microprocessor and a nanoprogrammed convolution computer is described. The processor was designed primarily for the implementation of adaptive filtering algorithms, and is controlled by a microprogram which resides in a writable control store. This primary microcode controls the operations performed by a bit-sliced ALU, the access to the data bus, I/O, memory access, and the initiation of the next lower level of microcode called nanocode. The convolution computer is implemented using two VLSI multiplier-accumulators, has two parallel data paths to memory which are independent of the main data bus, and has its own addressing logic. This allows convolutions to be done at an effective multiply-accumulation time of 100 nanoseconds per weight while the bit-slice ALU is doing I/O or computing parameters for the filter. The adaption algorithm is also implemented in nanocode in the convolution computer.