Debugging methodology for a synthesizable testbench FPGA emulator

Logic simulation provides SOC verification with full controllability and observability, but it suffers from very slow simulation speed for complex design. Using hardware emulation such as FPGA can have higher simulation speed. However, FPGA emulation approach has some limitations, i.e. unsynthesizable testbench and poor visibility for debugging. We address these problems by presenting a testbench synthesis engine as well as providing internal nodes probing on DUT. The proposed testbench synthesis engine is built by hardware constructs in terms of Verilog IEEE Simulation Model to correspond with testbench. Internal nodes are hardware-wired to DUT top-level during compilation, then sampled continuously by a sample logic into on-chip storage device (e.g. Block RAM, SDRAM and etc). Thus full observability can be achieved without stopping of DUT clock. Our experiment shows that, compared with a similar method in [13], simulation time is independent of number of probing nodes.