DocumentCode
3045190
Title
±1.5 V CMOS four-quadrant multiplier
Author
Li, Simon C.
Author_Institution
Dept. of Humanity & Sci., Nat. Yunlin Inst. of Technol., Touliu, Taiwan
fYear
1997
fDate
28-31 Jan 1997
Firstpage
429
Lastpage
432
Abstract
A low-voltage CMOS four-quadrant analogue multiplier using two NMOS operated in the triode region with modified bi-directional regulated cascode (RGC) structure is presented. The circuit can operate from a supply voltage of ±1.5 V. For a differential input voltage range up to ±0.8 V, this circuit has kept nonlinearity below 0.9% and total harmonic distortion less than 1%. The -3dB bandwidth of this multiplier is 15 MHz. The chip was fabricated in Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.8 μm Single-Poly-Double-Metal (SPDM) N-well process. The chip dissipates 24.4 mW and occupies 251×653 μm2 active area
Keywords
CMOS analogue integrated circuits; analogue multipliers; 0.8 mum; 1.5 to -1.5 V; 251 mum; 653 mum; CMOS four-quadrant multiplier; NMOS; TSMC; Taiwan Semiconductor Manufacturing Corporation; analogue multiplier; low-voltage; triode region; Bandwidth; Bidirectional control; CMOS technology; Circuits; Low voltage; MOS devices; MOSFETs; Signal processing; Total harmonic distortion; Transconductance;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific
Conference_Location
Chiba
Print_ISBN
0-7803-3662-3
Type
conf
DOI
10.1109/ASPDAC.1997.600283
Filename
600283
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