Probabilistic analysis of fault tolerance of FPGA switch block array

Summary form only given. We present a new approach for the evaluation of FPGA routing resources in the presence of faulty switches. Switch stuck-open faults (switch permanently off) as well as switch stuck-closed faults (switch permanently on) are addressed, which is directly related to fault tolerance of the interconnect for testing and reconfiguration at manufacturing and run-time application. Signal routing in the presence of faulty switches is analyzed at both switch block and array levels; probabilistic routing (mutability) is used as figure of merit for evaluating the programmable interconnect resources of FPGA architectures. Two approaches are proposed in this paper. The first approach is based on finding a permutation (one-to-one mapping) between the input and output endpoints. A probabilistic approach is also presented to evaluate fault tolerant routing for the entire FPGA by connecting switch blocks in chains as required for testing and to account for the I/O pin restrictions of an FPGA chip. The results are reported for various commercial and academic FPGA architectures.