Low power digital type ADC

Shrinking complementary metal-oxides-semiconductor (CMOS) technology has caused analog type analog-to-digital converters (ADCs) to face mounting challenges from reduced signal-to-noise ratio (SNR), lower intrinsic gain in CMOS devices, increased device leakage, larger transistor mismatches, and lower quality passives in lower transistor geometries. Digital functions instead have benefited from this technology scaling into smaller scales. Due to increased challenges of analog integration into these smaller scales, there is a drive to push these analog functions into the digital domain. Various digital type ADCs have been proposed, but such ADCs faced challenges from having large silicon area, and high power consumptions as compared to their analog counterparts. In this paper, we proposed to use Braun´s D-ADC [1] as the main approach to a low power digital type ADC. The approach to achieve low power is through gate count and frequency operation reduction. The proposed low power design is implemented and tested on field programmable gate arrays (FPGA), with a bandwidth of 20 kHz and achieving a SNR of -58 dB.