DocumentCode
3045534
Title
Automated wafer defect map generation for process yield improvement
Author
Tan, Cher Ming ; Lau, Kheng Tuan
Author_Institution
Sch. of EEE, Nanyang Technol. Univ. Singapore, Singapore, Singapore
fYear
2011
fDate
12-14 Dec. 2011
Firstpage
313
Lastpage
316
Abstract
Spatial Signature Analysis (SSA) is used to detect a reoccurring failure signature in today wafer fabrication. In order for SSA to be effective, it must correlate the signature to a wafer defect maps library. However, classifying the signatures for the library is time consuming and tedious. The Manual Visual Inspection (MVI) of several failure bins in a wafer map for multiple lots can lead to fatigue for the operator and resulted in inaccurate representation of the failure signature. Hence, an automated wafer map extraction process is proposed here to replace the MVI while ensuring accuracy of the failure signature library. Clustering tool namely Density-Based Spatial Clustering of Applications with Noise (DBSCAN) is utilized to extract the wafer spatial signature while ignoring the outliners. The appropriate size for the clustered signature is investigated and its performance is compared to the MVI signature. The analysis shows that for 3 selected failure modes, 20% occurrence rate clustered pattern provide similar performance to a 50% MVI signature. The proposed technique leads to a significant reduction in the time required for extracting current and new signatures, allowing faster yield response and improvement.
Keywords
electronic engineering computing; fault diagnosis; inspection; integrated circuit yield; pattern clustering; DBSCAN; apatial signature analysis; automated wafer defect map generation; density-based spatial clustering of applications with noise (; failure bins; failure signature; manual visual inspection; process yield improvement; wafer defect maps library; wafer fabrication; wafer spatial signature; Data mining; Educational institutions; Integrated circuits; Libraries; Noise; Software; Clustering; DBSCAN; Failure Bins; Library; SSA; Wafer Defect Map;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuits (ISIC), 2011 13th International Symposium on
Conference_Location
Singapore
Print_ISBN
978-1-61284-863-1
Type
conf
DOI
10.1109/ISICir.2011.6131959
Filename
6131959
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