Programmable space compaction for BIST

The authors address space compaction for built-in self-test (BIST). High quality BIST of modern complex VLSI circuits requires that large numbers of internal nodes be monitored during test. Unfortunately, area limitations typically preclude the association of observation latches for all the nodes of interest in the case where these are very numerous. Consequently, the process known as space compaction is increasingly required. A first contribution here is a taxonomy of test data compaction functions for BIST that uses space, time, memory, linearity, and circuit (functional) specificity as attributes. The major contribution is the introduction of a general class of space compactors called programmable space compactors (PSCs). Programmability enables highly effective space compactors to be designed for circuits under test (CUTs) subjected to a specific set of test patterns. The measures of effectiveness used to assess the PSCs are realizability, e.g., area, and error propagation performance. The authors develop a probabilistic error propagation model and propose a technique for selecting an effective PSC given the expected test data from a CUT and a probabilistic characterization of faulty CUT behaviors.