An all-digital DLL with dual-loop control for multiphase clock generator

This paper describes a low power and low area multiphase digital DLL. The architecture of the proposed DLL uses coarse tune loop and fine tune loop to reduce the static phase error and accomplish faster locking time. The DLL was designed using a 0.35 μm standard CMOS process with a 3.3V supply voltage. Simulation results show that the proposed DLL can generate four-phase clock signals ranging from 320 MHz to 500 MHz within a single cycle. At 500 MHz, the peak-to-peak jitter is 6 ps and the total power consumption is 28.3 mW. Moreover, the proposed DLL´s locking time is less than 24 clock cycles and the core area is 0.17 mm².