Model of on-chip VGP-CPW with P+ implant in CMOS process

Author

Wen, Jincai ; Lou, Jia ; Sun, Lingling

Author_Institution

Key Lab. for RF Circuits & Syst. of Minist. of Educ., Hangzhou Dianzi Univ., Hangzhou, China

fYear

2011

fDate

12-14 Dec. 2011

Firstpage

428

Lastpage

431

Abstract

This paper presents a vertical-ground-plane coplanar waveguide (VGP-CPW) line with P+ implant, and compared the characteristic parameters of transmission line with the general VGP-CPW structures. The ground plane connected to the substrate makes the proposed CPW line have higher isolation and lower characteristic impedance. The physical model of the VGP-CPW with P+ implant is presented as well as the general VGP-CPW line. Two different structures of transmission lines are fabricated in 65 nm 1P8M RF CMOS process and models are verified by the measured S-parameters up to 50 GHz.

Keywords

CMOS integrated circuits; coplanar transmission lines; coplanar waveguides; field effect MIMIC; 1P8M RF CMOS process; P+ implant; S-parameters; frequency 50 GHz; on-chip VGP-CPW model; size 65 nm; transmission line; vertical-ground-plane coplanar waveguide line; Coplanar waveguides; Implants; Integrated circuit modeling; Semiconductor device modeling; Solid modeling; Substrates; Transmission line measurements; CMOS; P+ implant; VGP-CPW; model;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits (ISIC), 2011 13th International Symposium on

Conference_Location

Singapore

Print_ISBN

978-1-61284-863-1

Type

conf

DOI

10.1109/ISICir.2011.6131988

Filename

6131988