Programmable low-dithering-jitter interpolator-based CDR

Author

Soh, Lip-Kai ; Wong, Wai-Tat ; Lee, Swee-Wah ; Khor, Chuan-Thim

fYear

2011

fDate

12-14 Dec. 2011

Firstpage

444

Lastpage

447

Abstract

This paper presents a methodology to determine the optimum filter settings for interpolator-based CDR. The proposed methodology quantifies the relationship between filter settings, latency of the CDR loop and input data frequency offset. A programmable interpolator-based CDR is designed to verify the proposed methodology. The CDR is implemented in TSMC 60nm LP CMOS technology. Measurement results show correlation between calculated results versus simulation and characterization results.

Keywords

CMOS digital integrated circuits; clock and data recovery circuits; digital filters; interpolation; jitter; programmable filters; CDR loop; TSMC LP CMOS technology; input data frequency offset; interpolator-based CDR; optimum filter settings; programmable digital filter; programmable low-dithering-jitter interpolator; size 60 nm; CMOS integrated circuits; Clocks; Detectors; Digital filters; Jitter; Solid state circuits; Clock data recovery; dithering;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits (ISIC), 2011 13th International Symposium on

Conference_Location

Singapore

Print_ISBN

978-1-61284-863-1

Type

conf

DOI

10.1109/ISICir.2011.6131992

Filename

6131992

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3046202