A Flipped Voltage Follower based low-dropout regulator with composite power transistor

This paper presents an improved design for the low-dropout regulator (LDO) based on the Flipped Voltage Follower (FVF) structure. A FVF based LDO regulator with composite power transistor (CPT) is proposed. It reduces the minimum biasing current requirement of the power transistor in Single-Transistor-Control (STC) LDO regulator whilst enhancing the loop gain as well as bandwidth performance. The proposed LDO regulator has been validated using GLOBALFOUNDRIES 0.18-μm CMOS process. Using the FVF STC structure as the benchmark, the simulation results have shown that the proposed CPT LDO regulator has a better load transient and accuracy than that of the STC and Buffered Flipped Voltage Follower (BFVF) counterpart whilst maintaining low voltage operation.