A VLSI speech analysis chip set based on square root normalized ladder forms

A VLSI (very large scale integration) chip set is presented that is based on the square root normalized ladder recursions developed by Lee and Morf [1]. It is shown that the equations are amenable to implementation using the so-called CORDIC (Coordinate Rotation Digital Computer) algorithms (see eq. [2]) because the time and order updates are easily representable as orthogonal transformations or rotations [7, 12]. An integrated implementation which exploits the concurrency of the ladder recursions together with possible hardware, speed and area tradeoffs are presented. The general applicability of the chip set to other signal processing tasks is demonstrated by showing that the discrete Fourier transform (DFT) is naturally suited to the architecture.