A 100 Mbit/s Viterbi decoder chip: novel architecture and its realization

Installing new high-speed digital microwave and satellite communication links often leads to the need for fast Viterbi decoders (VDs). However, the main unit of a VD contains a nonlinear data-dependent feedback loop that limits the maximum achievable throughput rate. A conventional realization of this loop leads to the problem that good decoder performance requires a large wordlength, whereas a high data rate requires a small wordlength. The authors present an architecture which eliminates this trade-off by bit-level parallel processing. The architecture was used in the design of a fabricated 115 Mb/s VD chip for an 8-PSK (phase-shift keying) trellis code. This represents the fastest single-chip VD built to date. The less complex design (<9000 gates) shows that the proposed architecture allows the single-chip realization of high-speed VDs with large wordlength and a larger number of states. It is shown that this architecture can also be applied to other related problems