FPGA based optimized SHA-3 finalist in reconfigurable hardware

A hash function is well-defined procedure to convert large, uncertain long message into fixed small integers. Secure Hash Algorithm (SHA) is an one-way message digest algorithm which is usually used in cryptographic applications such as authentication, digital signature and data integrity. In this paper, we proposed the reconfigurable structure for SHA-3 finalist BLAKE, Grostl, JH, Keccak and Skein, separately. The proposed reconfigurable Grostl, JH and Keccak could support different digested sizes. And Skein and BLAKE optimized three different modes using one single hardware core. The experimental results showed that our proposed structure could support different parameters of SHA-3 finalist with comparable performance among the existing works when ported to Xilinx Virtex-5 FPGA platform.