Live demonstration: The implementation of CMOS biopotential signal recording systems

In this demonstration, a CMOS biopotential signal recording system for electrocardiogram (ECG) and electroencephalogram (EEG) is presented. The system includes two individual chip modules of a multi-channel analog frond-end amplifier (AFEA) and a low-power successive approximation register analog-to-digital converter (SAR ADC). The AFEA consists of eight chopper-stabilized pre-amplifiers, an 8-to-1 analog multiplexer, and a programmable gain amplifier (PGA). The two chips are designed and fabricated by TSMC 0.18-um CMOS technology. The fabricated AFEA chip provides 40 to 74.1-dB tunable gain with 1-kHz to 7-kHz tunable low-pass cutoff frequency and 0.9-μVrm input referred noise. The measured SNDR of the SAR ADC is 56.68dB (53.89 dB) for Fin=10 Hz (7 kHz) with a power dissipation per channel of 2.95μW (5.82μW). The proposed system will be applied to different applications and demonstrated through internet monitoring and on-site demonstration.