An LSI chip set for DSP hardware implementation

This paper describes a new LSI chip set developed to provide a simple and cost-effective means for DSP hardware implementation. This chip set, consisting of two NMOS LSIs, contains enough logic and memory to perform such high level DSP functions as biquad filters and FFT butterflies at a high throughput rate, without any other external logic devices. It employs serial arithmetic and operates at a clock rate up to more than 5 MHz. Throughput rate can be traded-off with processing accuracy. Architecture is designed to pursue self-sufficient applicability to high level DSP functions, while retaining generality in application.