Title :
Static logic implication with application to redundancy identification
Author :
Zhao, Jian-Kun ; Rudnick, Elizabeth M. ; Patel, Janak H.
Author_Institution :
Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
fDate :
27 Apr-1 May 1997
Abstract :
This paper presents a new static logic implication algorithm. An improved implication procedure that fully takes advantage of the special context of static implication, the iterative method, and set algebra is described. The algorithm discovers at low cost many indirect implications which are not discovered by dynamic learning without tremendous time cost. The experimental results show that a very large number of indirect implications are found by our algorithm. The static implication procedure has many useful applications, one of which is static redundancy identification. Use of the static implications obtained from the algorithm in static redundancy identification for ISCAS85 combinational circuits resulted in a larger number of redundant faults identified than in previous methods
Keywords :
automatic test software; circuit analysis computing; fault diagnosis; identification; integrated logic circuits; iterative methods; logic testing; redundancy; indirect implications; iterative method; redundancy identification; redundant faults; set algebra; static learning algorithm; static logic implication; Algebra; Automatic test pattern generation; Circuit faults; Costs; Fault diagnosis; Forward contracts; Iterative algorithms; Iterative methods; Logic; Redundancy;
Conference_Titel :
VLSI Test Symposium, 1997., 15th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-7810-0
DOI :
10.1109/VTEST.1997.600290