An ISFET design methodology incorporating CMOS passivation

This paper presents a novel methodology for designing CMOS based Ion-sensitive Field-effect Transistors (ISFETs) taking into account the effects of passivation layer degradation. This allows more efficient implementation as well known challenges such as drift, threshold voltage variation, noise and dynamic range can be optimised through this methodology. By introducing a new term representing the influence of both chemical and electrical ISFET device dimensions, a more complete formulation is derived for current-voltage characteristics of the device. Using this, a potential 20% variation in sensing membrane that can result in up to 25% and 400% deviations respectively in trans-conductance and threshold voltage of the FET, can be suppressed to less than 1%. Furthermore this allows design of ISFETs which are less susceptible to variation due to drift. This ultimately allows proper and more accurate usage of ISFETs directly in processing circuitry rather than being used as stand alone sensors.