Title :
A process for fabricating high current circuits with high interconnect density
Author :
Law, H.H. ; Roy, A. ; Kossives, D. ; Wu, T.C. ; Bacon, D.D.
Author_Institution :
AT&T Bell Labs., Murray Hill, NJ, USA
Abstract :
Currently there is no cost-effective technology available for fabricating copper interconnect with thickness greater than 4 mils and large cross-sectional area. In opposition to the photoresist laminate manufacturer´s recommended procedure, a thick photoresist layer was achieved by laminating two layers sequentially on a substrate. Procedures for patterning, developing, and stripping die thick photoresist layer were developed. A process for making greater than 4 mil thick copper conductors with an aspect ratio of 1:1 in a 10 mil pitch has been ascertained and its feasibility demonstrated. The new process will give us a significant advantage in designing and producing high current circuits with high interconnect density requiring low conductor resistance for avoiding signal degradation and minimizing power dissipation
Keywords :
copper; etching; metallisation; photolithography; printed circuit manufacture; Cu interconnect; developing; high current circuit fabrication; high interconnect density; patterning; stripping; thick photoresist layer; two layer laminate; Conductors; Copper; Degradation; Integrated circuit interconnections; Laminates; Manufacturing; Power dissipation; Resists; Signal design; Signal processing;
Conference_Titel :
Electronics Manufacturing Technology Symposium, 1994. Low-Cost Manufacturing Technologies for Tomorrow's Global Economy. Proceedings 1994 IEMT Symposium., Sixteenth IEEE/CPMT International
Conference_Location :
La Jolla, CA
Print_ISBN :
0-7803-2037-9
DOI :
10.1109/IEMT.1994.404734