A high-quality and high-speed system of Bayer image restoration controlled by DM642 and FPGA

Author

Yang Haoyu ; Wang Lei ; Chen Shenghua ; Yuan Lingling ; Pan Xuan ; Ge Manling

Author_Institution

Key Lab. of Electromagn. Field & Electr. Apparatus Reliability, Hebei Univ. of Technol., Tianjin, China

Volume

2

fYear

2012

fDate

18-20 May 2012

Firstpage

935

Lastpage

938

Abstract

Here we present an efficient real-time system for Bayer image restoration. The system uses the dual processing pipeline architectures (DM642 and FPGA) to improve the speed and quality. FPGA collects and pre-processes a raw Bayer image from the CMOS image sensor. DM642 executes core algorithm processing and runs bilinear interpolation algorithm to form the RGB format image. The system could process a Bayer image of 752 × 480 pixels within 17.4 ms, and could transmit the final image to the host computer with 10 Mb/s band-width through the Ethernet port.

Keywords

Bayes methods; CMOS image sensors; field programmable gate arrays; image restoration; pipeline processing; real-time systems; Bayer image restoration; CMOS image sensor; DM642; Ethernet port; FPGA; RGB format image; bilinear interpolation algorithm; double chips; dual processing pipeline architectures; high-quality system; high-speed system; image processing; real-time system; CMOS integrated circuits; Clocks; Imaging; Interpolation; Noise; Process control; Read only memory; CMOS image sensor; DM642; FPGA; bilinear interpolation;

fLanguage

English

Publisher

ieee

Conference_Titel

Measurement, Information and Control (MIC), 2012 International Conference on

Conference_Location

Harbin

Print_ISBN

978-1-4577-1601-0

Type

conf

DOI

10.1109/MIC.2012.6273439

Filename

6273439