Title :
ChipEst-FPGA: a tool for chip level area and timing estimation of lookup table based FPGAs for high level applications
Author :
Xu, Min ; Kurdahi, Fadi J.
Author_Institution :
Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Abstract :
The importance of efficient area and timing estimation techniques for hierarchical design methodology is well-established in High-Level Synthesis (HLS), since the estimation allows more realistic exploration of the design space, and hierarchical design methodology matches well with HLS paradigm. In this paper, we present ChipEst-FPGA, a chip level estimator for designs implemented using a hierarchical design methodology for Lookup Table Based FPGAs. In FPGAs, the wire delay may contribute to a significant portion of the overall design delay. ChipEst-FPGA uses a realistic model which takes the component area/delay as well as wiring effects into account. We tested our ChipEst-FPGA on several benchmarks and the results show that we can get accurate area and timing estimates efficiently
Keywords :
circuit layout CAD; field programmable gate arrays; high level synthesis; ChipEst-FPGA; FPGAs; High-Level Synthesis; area and timing estimation; chip level estimator; hierarchical design methodology; lookup table based FPGAs; wire delay; Circuit testing; Delay; Design methodology; Field programmable gate arrays; High level synthesis; Process design; Routing; Table lookup; Timing; Wire;
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific
Conference_Location :
Chiba
Print_ISBN :
0-7803-3662-3
DOI :
10.1109/ASPDAC.1997.600292