A DFT technique for analog-to-digital converters with digital correction

Pipeline or sub-ranging architectures enable the implementation of high-speed, low-power and high-resolution Analog-to-Digital Converters (ADCs). It is usual in these architectures to include digital correction to reduce the sensitivity to certain component nonlinearities, such as comparator offsets and settling errors. However, digital correction makes difficult the detection of defective operation because some errors could not be revealed in the output code under nominal test conditions but could appear when operation conditions change. This paper presents a Design-for-Testability (DFT) technique for concurrent error detection in digitally-corrected pipelined ADCs. The approach is based on hardware redundancy, requiring an additional sub-DAC, a window comparator and some control logic. The effectiveness of the technique has been evaluated by means of fault simulations in a switched-capacitor 10-bit ADC application example