DocumentCode
3047758
Title
A family of high speed, floating point arithmetic chips
Author
Schirm, Louis, IV
Author_Institution
TRW, LSI Products, San Diego, Calif.
Volume
6
fYear
1981
fDate
29677
Firstpage
374
Lastpage
377
Abstract
VLSI technology has been rapidly driving down the cost per function of digital signal processing. Indeed, the functions being built today in one box or one rack using modern IC´s would have been economically or physically impossible just a few years ago (i.e. 300MHZ, 1 million point real time FFT). This same technology has opened the door to larger, more complex, algorithms to solve bigger problems--such as image processing or voice recognition. These newer algorithms require in some cases greater precision, but more often, greater dynamic range in the calculations than that possible with the older fixed point machines. This paper describes four VLSI circuits needed to drive down the cost of high speed floating point arithmetic.
Keywords
Circuits; Cost function; Digital signal processing chips; Dynamic range; Floating-point arithmetic; Image processing; Image recognition; Signal processing algorithms; Speech recognition; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '81.
Type
conf
DOI
10.1109/ICASSP.1981.1171310
Filename
1171310
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