A new design technique for low power subthreshold logic circuits with enhanced robustness against process variations

Author

Majidi, Saeed ; Maymandi-Nejad, Mohammad

Author_Institution

Ferdowsi Univ. of Mashhad, Mashhad, Iran

fYear

2013

fDate

14-16 May 2013

Firstpage

1

Lastpage

4

Abstract

Designing logic circuits in the subthreshold regime is one of the most effective ways to reduce the power consumption of digital circuits. In the subthreshold region, the current is an exponential function of the threshold voltage and the behavior of transistors is more susceptible to process variations. In this paper, we present a new design technique that helps reduce the impact of process variations on the circuit. The proposed technique is implemented on the static C2MOS flip-flop and the flip flop is used in a shift register. The circuit is simulated in the 90nm CMOS technology using a 0.2V supply voltage. Simulation results show that the robustness of the circuit is improved while the power consumption and the area are kept at minimum.

Keywords

CMOS logic circuits; flip-flops; logic design; low-power electronics; CMOS technology; digital circuits; exponential function; low power subthreshold logic circuit design technique; power consumption; process variations; shift register; size 90 nm; static CMOS flip-flop; subthreshold regime; transistor behavior; voltage 0.2 V; CMOS integrated circuits; Clocks; Inverters; Power demand; Shift registers; Threshold voltage; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Engineering (ICEE), 2013 21st Iranian Conference on

Conference_Location

Mashhad

Type

conf

DOI

10.1109/IranianCEE.2013.6599690

Filename

6599690