A new design technique for low power subthreshold logic circuits with enhanced robustness against process variations

Designing logic circuits in the subthreshold regime is one of the most effective ways to reduce the power consumption of digital circuits. In the subthreshold region, the current is an exponential function of the threshold voltage and the behavior of transistors is more susceptible to process variations. In this paper, we present a new design technique that helps reduce the impact of process variations on the circuit. The proposed technique is implemented on the static C2MOS flip-flop and the flip flop is used in a shift register. The circuit is simulated in the 90nm CMOS technology using a 0.2V supply voltage. Simulation results show that the robustness of the circuit is improved while the power consumption and the area are kept at minimum.