Title :
An FPGA-based Sudoku Solver based on Simulated Annealing methods
Author :
Malakonakis, Pavlos ; Smerdis, Miltiadis ; Sotiriades, Euripides ; Dollas, Apostolos
Author_Institution :
Dept. of Electron. & Comput. Eng., Tech. Univ. of Crete, Chania, Greece
Abstract :
The Sudoku simulated annealing solver -SSAS is a probabilistic Sudoku solver. The general design is capable of solving a Sudoku board of order up to fifteen (15 × 15 × 15 × 15). It has been designed and fully implemented on a Xilinx Virtex II Pro - based Digilent XUP board. The solver has a serial-port interface to download problems and upload results to a personal computer, according to the specifications of the relevant competition of the 2009 International Conference on Field Programmable Technology (FPT). The SSAS has solved in actual hardware Sudoku puzzles of up to order 12 within the competition-imposed time limits.
Keywords :
computer interfaces; field programmable gate arrays; games of skill; probability; simulated annealing; Digilent XUP board; FPGA-based Sudoku solver; Xilinx Virtex II Pro; hardware sudoku puzzles; personal computer; probabilistic sudoku solver; serial-port interface; simulated annealing methods; sudoku board; sudoku simulated annealing solver; Computational modeling; Computer simulation; Explosions; Field programmable gate arrays; Hardware; Laboratories; Microcomputers; Microprocessors; Simulated annealing; Testing;
Conference_Titel :
Field-Programmable Technology, 2009. FPT 2009. International Conference on
Conference_Location :
Sydney, NSW
Print_ISBN :
978-1-4244-4375-8
Electronic_ISBN :
978-1-4244-4377-2
DOI :
10.1109/FPT.2009.5377608
