Title :
Using a reconfigurable compute cluster for the acceleration of neural networks
Author :
Pohl, Christopher ; Hagemeyer, Jens ; Romoth, Johannes ; Porrmann, Mario ; Rückert, Ulrich
Author_Institution :
Syst. & Circuit Technol., Univ. of Paderborn, Paderborn, Germany
Abstract :
In this paper we present the RAPTOR family as an advanced modular platform for both FPGA-based rapid prototyping and hardware acceleration. Using modern FPGAs and high speed communication links, performance and flexibility of the approach will be shown by means of Kohonens self-organizing map algorithm. This highly parallel algorithm is partitioned onto several FPGAs in different system environments, such as to demonstrate the scalability and the flexibility of the proposed platforms.
Keywords :
field programmable gate arrays; self-organising feature maps; FPGA-based rapid prototyping; Kohonens self-organizing map algorithm; RAPTOR family; hardware acceleration; high speed communication links; neural networks; reconfigurable compute cluster; Acceleration; Artificial neural networks; Clustering algorithms; Computer networks; Emulation; Field programmable gate arrays; Hardware; Neural networks; Partitioning algorithms; Prototypes;
Conference_Titel :
Field-Programmable Technology, 2009. FPT 2009. International Conference on
Conference_Location :
Sydney, NSW
Print_ISBN :
978-1-4244-4375-8
Electronic_ISBN :
978-1-4244-4377-2
DOI :
10.1109/FPT.2009.5377611
